1. Field of the Invention
The present invention relates to a contact interface within a contact opening for a shallow junction device, which contact interface is in electrical communication with an active surface of a semiconductor substrate, and methods of forming the same. More particularly, the present invention relates to altering an Ionized Metal Plasma ("IMP") process to form a contact interface having a substantially continuous profile along sides of a depression formed in the active surface of the semiconductor substrate, wherein the depression is formed by an etching process to form a contact opening through a dielectric layer.
2. State of the Art
In the processing of integrate circuits, electrical contact must be made to isolated active-device regions formed within a semiconductor substrate, such as a silicon wafer. Such active-device regions may include p-type and n-type source and drain regions used in the production of NMOS, PMOS, and CMOS structures for production of DRAM chips and the like. The active-device regions are connected by conductive paths or lines which are fabricated above an insulative or dielectric material covering a surface of the semiconductor substrate. To provide electrical connection between a conductive path and active-device regions, openings in the insulative material are generally provided to enable a deposited conductive material to contact the desired regions, thereby forming a "contact". The openings in the insulative material are typically refereed to as "contact openings".
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are goals of the computer industry. However, as components become smaller and smaller, tolerances for all semiconductor structures (such as circuitry traces, contacts, and the like) become more and more stringent. In fact, each new generation of semiconductor device technology has seen a reduction in contact size of, on average, about 0.7 times. Unfortunately, interconnect delays have also increased at a rate of about two times per each new generation. Interconnect delays have a limiting effect on clock speeds which lowers performance. Although the reduction in size creates technical problems, the future advancement of the technology requires the capability for forming sub-0.25 .mu.m contact openings with aspect ratios (height to width) as high as 8 to 1.
Moreover, the reduction in contact size (i.e., diameter) has resulted in interable increases in resistance between the active-device regions and the conductive material. Various methods have been employed to reduce the contact resistance at the interface between the conductive material and active-device region. One such method includes the formation of a metal silicide contact interface atop the active-device region within the contact opening prior to the application of the conductive material into the contact opening. A common metal silicide material formed is titanium silicide (TiSi.sub.x, wherein x is predominantly equal to 2) generated from a deposited layer of titanium.
FIGS. 7-11 illustrate a conventional method of forming a titanium silicide layer on an active-device region. FIG. 7 illustrates an intermediate structure 300 comprising a semiconductor substrate 302 having an active-device region 304 formed therein with a dielectric layer 306 disposed thereover. A contact opening 308 is formed, by any known technique, such as patterning of a photoresist and subsequent etching, in the dielectric layer 306 to expose a portion of the active-device region 304, as shown in FIG. 8. A thin layer of titanium 310 is applied over the dielectric layer 306 and the exposed portion of the active-device region 304, as shown in FIG. 9. A high temperature anneal step is conducted in an inert atmosphere to react the thin titanium layer 310 with the active-device region 304 in contact therewith which forms a titanium silicide layer 312, as shown in FIG. 10. The non-reacted titanium layer 310 may then be removed to result in a final structure 314 with a titanium silicide layer 312 formed therein, as shown in FIG. 11.
Naturally, as contact opening aspect ratios increase, thicker conductive material layers must be deposited, usually by DC magnetron sputtering, to obtain the required amount and depth of conductive material on the active-device region at the bottom of the contact opening. However, with contact openings approaching dimensions of 0.25 .mu.m in diameter and aspect ratios of greater than 4 to 1, currently utilized processing techniques, such as physical vapor deposition, do not provide adequate step coverage for depositing conductive materials. Even the use of filtering techniques, such as physical collimated deposition and low-pressure long throw techniques, which are used to increase the number of sputtered particles contacting the bottom of the contact opening, have proven ineffective for contact opening diameters less than about 0.35 .mu.m (for 0.25 .mu.m diameter contact opening, the deposition efficient is less than about 15%) and as contact opening aspect ratios increase beyond about 3 to 1 (bottom step coverage of less than 20%). Both collimated deposition and low-pressure long throw techniques also tend to create excessive film buildup at the top corner or rim of the contact opening, causing shadowing of bottom corners of the contact openings. The result is little or no deposited film at the bottom corners of the contact opening and consequently poor step coverage. Although increasing collimator aspect ratio results in improved step coverage, it also reduces deposition rate which reduces product throughput and, in turn, increases the cost of the semiconductor device.
Recently, physical vapor deposition ("PVD") has been revived with the introduction of the Ionized Metal Plasma ("IMP") process. Ionizing sputtered metal particles allows for highly directional PVD for depositing material in contact openings with up to about 6 to 1 aspect ratios and having 0.25 .mu.m diameter openings. The IMP process can result in up to about 70% bottom coverage and up to about 10% sidewall coverage, even with such high aspect ratios and small diameter contact openings.
As illustrated in FIG. 12, an apparatus 320 used in the IMP process consists of a deposition chamber 322 having a pedestal 324 to support a semiconductor substrate 326 to be coated and a target 328, such as a titanium plate. The pedestal 324 has an RF power bias 330, the deposition chamber 322 includes an RF power source 332, and the target 328 has an RF or a DC power source 334.
In the IMP process, metal particles (atoms, ions, etc.) (not shown) are sputtered from the target 328. These metal particles pass through a high-density plasma 336 (e.g., usually between about 10.sup.11 /[cm.sup.3 ] and 10.sup.12 /[cm.sup.3 ]) formed between the target 328 and semiconductor substrate 326 where they become ionized. The ionization of the material particles enables a user to control the angular distribution of material arriving at the substrate for maximum bottom coverage in the bottom of the contact openings (not shown) by the manipulation of the electric field at the substrate.
In the deposition chamber 322, the plasma 336 is maintained by inductively coupling RF energy from the RF power source 332 into the plasma 336. An electric field, or bias voltage, develops in a sheath layer 338 around the plasma 336, accelerating the metal ions (not shown) in a vector substantially perpendicular to the semiconductor substrate 326 by electrostatic coupling. The potential difference between the plasma 336 and the semiconductor substrate 326 can be optionally modulated by applying independent bias power from the pedestal power bias source 330 to the semiconductor substrate 326.
The degree of ionization of sputtered metal particles depends on their residence time in the plasma 336 (i.e,. the longer the residence time, the greater the ionization). The sputtered atoms are ejected from the target 328 with relatively high energies (1 eV to 10 eV), leading to very short residence times. In order to slow down the metal particles for higher ionization, the process is usually operated at relatively high pressure (greater than about 10 mtorr). Such a pressure regime is higher than the 0.5-10 mtorr normally encountered in traditional PVD processes.
One drawback of the IMP process is the uniformity of the thickness of material deposited in the contact opening. When a contact opening is formed, a portion of the active material is also removed, as shown in FIG. 13. Elements common between FIGS. 7-11 and FIGS. 13 and 14 retain the same numeric designation. The uniformity of the IMP process results in a substantially level layer of conductive material 342 at the bottom 344 of the contact opening 308 with very little or no sidewall coverage at the active-device region 304. Thus, when a titanium silicide layer 346 is formed by a high temperature anneal, the titanium silicide layer 346 formed does not effectively take advantage of the sidewall portions 348 which had little or no conductive material 342 thereon (see FIG. 13).
This uniformity is particularly troublesome with shallow junction devices. As semiconductor devices become smaller in lateral dimension, they also become smaller in vertical dimension. Thus, shallow junction formation techniques are used to reduce the depth of the active-device regions of the semiconductor devices. However, for active device regions having a depth of less than 0.15 microns, a contact depth into the active-device region without current leakage into the underlying substrate requires less than 600 .ANG. of junction penetration for n-type active-device regions and less than about 800 .ANG. for p-type active-device regions. Junction penetration includes both the penetration of the silicide and the depth of active-device region removed during the etching of the contact opening.
FIG. 15 illustrates a contact opening 308 formed to contact a shallow active device region 350. Elements common between FIGS. 13 and 14 and FIGS. 15 and 16 retain the same numeric designation. Again, when a contact opening 308 is formed, a portion of the active material is also removed, as shown in FIG. 15. The uniformity of the IMP process results in a substantially level layer of conductive material 342 at the bottom 352 of the contact opening 308 with very little or no sidewall coverage at the shallow active-device region 350. Thus, when a titanium silicide layer 346 is formed by a high temperature anneal, the titanium silicide layer 346 formed does not form on the sidewall portions 348 of the contact opening, which had little or no conductive material 342 thereon (see FIG. 15), and the titanium silicide layer 346 can extend past the shallow active-device region 350 which causes junction leakage (escape of current from the shallow active-device region) into the underlying substrate material.
Thus, it can be appreciated that it would be advantageous to develop a technique and a contact interface to maximize sidewall coverage of the exposed active-device region while minimizing bottom coverage of the exposed active-device region in a contact opening to form a contact interface for a shallow junction device.